FIG. 1 shows a high-level block diagram of the layout of a conventional field-programmable gate array (FPGA) 100 having a logic core 102 surrounded by an input/output (I/O) ring 104. Logic core 102 includes an array of programmable logic blocks (PLBs) 106 (also referred to in the art as programmable logic cells, logic array blocks, or configurable logic blocks) intersected by rows of block memory 108. Each PLB contains circuitry that can be programmed (i.e., configured) to perform a variety of different functions. The memory blocks in each row are available to store data to be input to the PLBs and/or data generated by the PLBs. I/O ring 104 includes sets of I/O buffers 110 programmably connected to the logic core by multiplexer/demultiplexer (mux/demux) circuits 112. The I/O buffers support external interfacing to FPGA 100. Also located within the I/O ring are a number of phase-locked loop (PLL) circuits 114 that are capable of providing different timing signals for use by the various elements within FPGA 100. Those skilled in the art will understand that FPGAs, such as FPGA 100, will typically include other elements, such as additional configuration memory, that are not shown in the high-level block diagram of FIG. 1. In addition, general routing resources, including clocks, buses, general-purpose routing, high-speed routing, etc. (also not shown in FIG. 1), are provided throughout the FPGA layout to programmably interconnect the various elements within FPGA 100.
The layout of FPGA 100 comprises multiple instances of a limited number of different types of blocks of circuitry. For example, I/O ring 104 contains a number of instances of the same basic block of programmable I/O circuitry repeated around the periphery of the device. Similarly, each PLB 106 within logic core 102 may be implemented using a different instance of the same set of programmable logic circuitry. Furthermore, each row of block memory 108 may contain one or more instances of the same block of memory that may be designed, for example, for use as configuration memory for the FPGA.
FIG. 2 shows a schematic block diagram of an exemplary conventional block 200 of configuration memory for use in an FPGA, such as FPGA 100 of FIG. 1. Configuration memory block 200 includes three rows 202–206 of static random-access memory (SRAM) cells and a shift register 208 formed by three flip-flops (FFs) SR1–3 connected in cascade.
Shift register 208 enables the rows of SRAM cells in block 200 to be sequentially accessed starting with row 202, followed by row 204, and lastly row 206. In particular, when a one-clock-cycle pulse is applied to address line ADD0, the pulse, which is applied at the D input of FF SR1, will appear at the Q output of FF SR1 at the next rising edge of clock CK, which applies the pulse both to the address ports ADD of the SRAM cells in row 202 (thereby enabling access to those SRAM cells) as well as to the D input of FF SR2. At the next rising edge of clock CK, the pulse will appear at the Q output of FF SR2, which applies the pulse both to the address ports ADD of the SRAM cells in row 204 as well as to the D input of FF SR3. At the next rising edge of clock CK, the pulse will appear at the Q output of FF SR3, which applies the pulse to the address ports ADD of the SRAM cells in row 206.
Exemplary configuration memory block 200 includes two different types of SRAM cells: single-port memory cells that are used only for configuration operations (e.g., storing configuration data used to control configuration multiplexers (muxes) in the FPGA) and dual-port memory cells that can be used for either configuration data storage or local data storage (e.g., storing so-called “local” data associated with user data-processing operations of the FPGA that are not related to configuration operations). In particular, rows 202 and 206 contain only single-port memory cells (labeled “mc” in FIG. 2), while row 204 includes both single-port memory cells and dual-port memory cells (labeled “dp mc”).
As represented for the single-port memory cells in row 202 of FIG. 2 (but which in fact applies to all of the single-port memory cells in block 200), the Q output of each single-port memory cell is connected to the control port SD of a different configuration mux 210 to control whether the value at the mux's data input D0 or the mux's data input D1 is presented at the mux's data output Z.
FIG. 3 shows a schematic diagram of a typical SRAM memory cell 300 that can be used to implement each single-port memory cell in configuration memory block 200 of FIG. 2. If address line ADD is high, then transistors 302 and 304 (e.g., MOSFETs) are on, enabling one bit of configuration data appearing as complementary signals on input data lines DATA, DATAN to be stored in latch 306 and presented at the memory cell's output port, labeled MUX_CONTROL. If address line ADD is low, then transistors 302 and 304 are off, and latch 306 retains its previously stored value and continues to present that value at the cell's output port MUX_CONTROL. Note that, for each single-port memory cell in the higher-level block diagram of FIG. 2, the configuration-data input ports DATA and DATAN of FIG. 3 are not shown in FIG. 2, and the Q output in FIG. 2 is the output port MUX_CONTROL of FIG. 3.
Referring again to FIG. 2, memory cell 212 is one of the four dual-port memory cells in row 204 of configuration memory block 200. In addition to the complementary configuration-data input ports (which are not shown in FIG. 2), dual-port memory cell 212 also has a local-data input port DIN. As mentioned above, dual-port memory cell 212 supports two different functions: (1) storage of configuration data used to control a configuration mux and (2) storage of local data.
The storage of configuration data is accomplished in the same manner as for the single-port memory cells. In particular, if row address line ADD2 is high, then one bit of configuration data can be written into memory cell 212 for use in controlling a configuration mux, in this case, configuration mux 214.
If memory cell 212 is not needed to store configuration data (e.g., memory cell 212 had previously been used to store configuration data, but is no longer needed to store that configuration data), then memory cell 212 is available for use in storing local data. As represented in FIG. 2, local-data mux 216 provides (1) one bit of local data (LOCAL_DATA_IN) to the Q port of memory cell 212 via transistor gate 218 and (2) an inverted version of that local-data bit to the DIN port of memory cell 212 via inverter 220 and transistor gate 222, where configuration mux 224 provides local address signal LOCAL_ADD, which determines whether or not that bit of local data is written into memory cell 212. Moreover, in addition to being connected to the control input of configuration mux 214, the Q output of memory cell 212 is also connected to the D0 input port of configuration mux 226.
If row address line ADD2 is low and if local address line LOCAL_ADD is high, then the local-data bit LOCAL_DATA_IN from local-data mux 216 will be stored in memory cell 212. In order to speed up this local data processing, in addition to the stored local-data bit being applied to the D0 input of configuration mux 226 via memory cell output port Q, the local-data bit is also applied (more) directly to that D0 input via transistor gate 218. If both row address line ADD2 and local address line LOCAL_ADD are low, then the previously stored value in memory cell 212 is applied to both the control input SD of configuration mux 214 and the D0 input of configuration mux 226, whether that previously stored value was configuration data or local data.
FIG. 4 shows a schematic diagram of a typical SRAM memory cell 400 that can be used to implement each dual-port memory cell in configuration memory block 200 of FIG. 2, such as memory cell 212. Note that, in addition to memory cell 400, FIG. 4 shows inverter 220 and transistor gates 218 and 222 of FIG. 2.
Dual-port memory cell 400 has two address lines: (1) configuration address line ADD, which controls configuration-data transistor gates 402 and 404, and (2) local address line LOCAL_ADD, which controls local-data transistor gates 218 and 222. Dual-port memory cell 400 also has two sets of input ports: (1) complementary configuration-data input ports DATA and DATAN, which are applied to latch 406 via gates 402 and 404, and (2) local-data input port LOCAL_DATA_IN, whose value is applied to latch 406 via inverter 220 and gates 218 and 222. As such, ports Q and DIN may be considered to be a pair of complementary local-data input ports for memory cell 400.
Note that, for memory cell 212 in the higher-level block diagram of FIG. 2:                Configuration-data input ports DATA and DATAN of FIG. 4 are not shown in FIG. 2;        Configuration address line ADD2 in FIG. 2 is configuration address line ADD of FIG. 4; and        The Q output in FIG. 2 is both the output port MUX_CONTROL and the output port LOCAL_DATA_OUT of FIG. 4.        
Note further that the additional circuitry of dual-port memory cell 400 of FIG. 4 (as compared with that of single-port memory cell 300 of FIG. 3) enables a single bit of local data to be written into memory cell 212 of FIG. 2 without having to access all of the memory cells in row 204 using configuration address line ADD2.
In a typical block of configuration memory, such as block 200 of FIG. 2, memory cells are arranged in rows and columns, where the memory cells in each row share the same address line (e.g., ADDi of FIG. 2) and the memory cells in each column share the same complementary pair of configuration data lines (e.g., DATA and DATAN of Figs. B and C). The capacitance on the configuration-data input ports (i.e., DATA and DATAN) of each SRAM memory cell, such as either memory cell 300 of FIG. 3 or memory cell 400 of FIG. 4, is a function of the number of memory cells in each column. Configuration memory blocks having larger number of rows will have memory cells with higher capacitances. These high capacitances limit the speeds at which data can be written into the memory cells, when corresponding address line ADDi is high. Since relatively slow configuration operations are acceptable (e.g., 20 MHz for configuration access vs. 400 MHz for local access), the typical high capacitance levels on DATA and DATAN are tolerable for configuration writes, but not for local data writes.
Conventional FPGAs perform soft error-detection operations, in which the data stored in memory is periodically read in order to verify that the data is correct. When such operations are implemented for configuration memory block 200 of FIG. 2, rows 202–206 will typically be sequentially accessed via configuration address lines ADD1–ADD3, with the data stored in the corresponding memory cells being sensed via signal lines DATA and DATAN (of FIGS. 3 and 4).
It is possible, during such soft error-detection operations, for configuration address line ADD2 to be high at the same time that an attempt is being made to write local data into memory cell 212 (i.e., local address line LOCAL_ADD is also high). In that case, the high capacitance at ports DATA and DATAN can inhibit the ability to quickly or even successfully write the desired bit of local data into memory cell 212.
Moreover, FPGAs can be subjected to partial reconfiguration, during which portions of the configuration memory are reprogrammed (i.e., stored with new configuration data). During such partial reconfiguration, local data stored in dual-port memory cells, such as memory cell 212 of FIG. 2, may be lost.